1. Field of the Invention
The present invention relates generally to electrical circuits, and more particularly but not exclusively to power factor correction.
2. Description of the Background Art
Power factor is the ratio of real power to apparent power delivered to a load, represented as a number between 0 and 1. Generally speaking, a load with low power factor draws more power than a load with high power factor. As its name implies, power factor correction (PFC) involves correcting the power factor of a load to a high value, which is ideally as close to 1.0 as possible. High power factor is achieved when the input current of a power supply is sinusoidal and in phase with the line voltage. A PFC converter shapes the input current to achieve almost unity power factor.
Boundary conduction mode (BCM) (also known as “critical conduction mode”) boost PFC converters have been widely used in low power applications because they are more efficient and cost effective than continuous conduction mode (CCM) boost PFC converters. These benefits result from elimination of reverse-recovery losses of the boost diode and turning ON the boost switch with zero-voltage switching (ZVS) or near ZVS (also referred to as “valley switching”). However, the BCM approach exhibits a relatively large peak inductor current, which is twice of its average value and accordingly requires a larger differential mode electro-magnetic interference (EMI) filter than the CCM approach. This offsets the benefits of the BCM approach, limiting the applicable practical power level of BCM PFC circuits below 300 W.
Recently, interleaved BCM PFC circuits have become more popular because of their ability to reduce the input current ripple and, consequently, the size of the EMI filter, extending their applicable practical power level above 300 W. In addition, the output current ripple can be also significantly reduced by the ripple cancellation effect of interleaving, which allows longer life time of the output capacitor. Another benefit of the interleaving approach is that light load efficiency can be improved by shutting down one channel of interleaved converters at light load condition. This is known as “phase management.” By shutting down one of parallel connected converters, the switching loss and MOSFET gate drive loss can be reduced to improve energy efficiency at light load conditions.
The present invention provides phase management to interleaved PFC circuits to minimize line current distortion during adding or shedding of channels. This is particularly important in display applications, such as televisions and computer monitors, where glitch in the line current may result in visible noise on the screen. The present invention also allows small hysteresis for the phase management threshold regardless of the ripple of compensation voltage, resulting in tight control of the power level for channel adding and shedding. The present invention may be employed in currently available or new interleaved PFC circuits.